Automatic Transformation of System Models in Automotive Electronics
نویسندگان
چکیده
Evaluation and refinement of system models often require modifications in the model that follow concrete rules. In this work, a method for a flexible automation of such transformation steps will be presented. It allows savings in development time and reduces the error proneness. Therefore, a tool for rule based manipulation of VHDL design descriptions has been extended to enable its use with system models in C++ and SystemC. An automotive electronics application, the integration of SystemC modules into a MATLAB/Simulink simulation by automatic wrapper generation, will show its use in the design process.
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